1. Field of the Invention
The present invention relates generally to computer systems with internal operational speeds and components that impose timing constraints on clock and control signals distributed about the system. More particularly, the present invention relates to a topology for a flexible system for adjusting clock and control signal path lengths and therefore signal timing adjustments.
2. Background of the Invention
Modern computer systems are a conglomeration of components. Each component is designed and/or programmed to perform one or more specific tasks. However, for overall operation of the computer system to be successful, those various components must communicate with one another and exchange information. That exchange of information could be of data related to the particular application running on the system, or could be instructions of the software program itself moved from mass storage devices or random access memory to the microprocessor for execution. Regardless of the receiving and sending device in any transfer of data or programs, there must be some coordination between the devices to make sure that information is exchanged at the proper times.
Exchange of information in modem computer systems is typically completed by the exchange of a block of information in a synchronous manner. That is, modem computer system components are interconnected by a series of bus structures capable of transmitting a predefined amount of data at any one time, e.g., 64 bits of information at a time. The “synchronous” descriptor means that the exchange of information between a sending device and a receiving device is done at predefined times typically based upon a host clock signal that is available for all the components of the computer system to use as a time reference.
As computer microprocessor and bus transfer speeds increase, factors such as the speed of propagation of signals within the computer begin to come into play. For purposes of illustration, consider the generic transfer of information depicted in FIG. 1 from a sending device 2 to a receiving device 4 along an arbitrary bus 6. Although the propagation of electrical signals along wires and traces of printed circuit boards is extremely fast, on the order of one inch in every 200×10−12 seconds (200 pico-seconds (ps)), the speed is finite. Thus, in the generic system of FIG. 1, the information driven to the bus 6 by the sending device 2 is not instantaneously available at the receiving device 4; rather, the availability of the data driven by the sending device 2 at the receiving device 4 is, in part, a function of the distance between those two devices. Thus, if the sending device clock 8 and the receiving device clock 10 in FIG. 1 are exactly in phase (rise and fall at exactly the same time), and there is a fairly significant distance between the two devices (on the order of several inches on a computer circuit board), then the exchange of information will not occur if the sending device 2 drives on the leading edge of the send clock 8 and the receiving device simultaneously tries to read that information on the rising edge of the read clock 10. To compensate for such a situation, and referring to FIG. 2, related art devices compensate for propagation delay, among other things, by shifting or skewing the clocks between the sending and receiving devices. With regard to the generic transfer of information between the sending device 2 and the receiving device 4 of FIG. 1, related art devices shift in time the read clock away from the send clock as exemplified in FIG. 2. That is, the send clock and the read clock have the same frequency but are shifted in phase such that there is a finite amount of time ΔT between the rising edge of the send clock and the rising edge of the read clock. This amount of time ΔT is sufficient to allow the signals driven by the sending device to onto the bus 6 to propagate along the length of the bus and become available at the receiving device 4.
In the design of motherboards and other computer system components, it is usually not known in advance the exact timing required between particular devices or components. That is, a board designer may known the distance between a bridge device and a main memory device, for example, but that designer may not know the timing constraints of the particular components to be installed. In the related art, some designers compensated for this lack of knowledge at the design phase of the board by designing in clock signal paths having varying lengths. Once the components are installed, or the timing constraints otherwise determined, the particular clock signal path which meets the timing constraints of the particular system is used. FIG. 3 shows one related art method for adjusting the signal path lengths for a system clock. In particular, FIG. 3 shows a clock source 12 coupled to a clock destination 14 by way of a plurality of clock paths 16 (for the shorter path) and 18 (for the longer path). In such a system, each of these paths 16 and 18 are designed onto the printed circuit board in advance, not knowing which path represents the correct signal timing delay for the components of the system. Once the individual components are identified and testing performed on the board, the particular path that represents the signal path length closest to what was needed in the system is selected jumpering, by one of several known techniques, the connections at each end of the path desired. More particularly, the connections 20 and 22 would be electrically connected to allow the clock source to propagate along the shorter path 16, if that was the desired path, and jumpers 24 and 26 would be connected if the signal path length along the longer path 18 is desired.
However, related art implementation such as that shown in FIG. 3 have several problems. First, in such a design there are only two possible signal path lengths. Thus, such a system would not compensate for the situation where the optimum signal path length is somewhere between the short path 16 and the long path 18 lengths. In such a situation, system designers typically choose the shorter path length and compensate by adding capacitance. Adding capacitance, while having the effect of slowing the rise times associated with that clock, may only be used to a certain extent before clock signal degradation becomes a problem.
Secondly, if the system of FIG. 3 is used, there are several dead-end paths, or stubs, that the propagating clock signal may take. For example, the clock signal propagates from the clock source 12 out to the branch point 28. If it is assumed that the short path length is selected and jumpers are placed at locations 20 and 22 to complete the short path circuit, some of the clock signal propagates toward the open jumper 24 and reflects at that location back toward the clock signal. Likewise this occurs at the other end with regard to the open jumper location 26. These reflecting waves interfere with the clock signal and cause signal degradation.
Finally, printed circuit board space on motherboards, and the like, is a premium, thus not allowing a system designer the capability of designing in several clock paths, e.g., nine or more, from which to choose later on.
Thus, what is needed in the art is a flexible and precise signal timing adjustment system that gives the system designer the maximum number of possible signal path lengths without the draw backs of using an inordinate amount of circuit board space, and without the detrimental effects associated with interference of electromagnetic signals based on reflection in stub circuits.